A comparison of CVD stacked gate oxide and thermal gate oxide for 0.5- mu m transistors subjected to process-induced damage

Abstract

Process-induced damage of gate oxide or of the Si-SiO/sub 2/ interface may result in device degradation problems such as threshold voltage scatter. The problem is especially pronounced for submicrometer technology. In addition to offering a low area defect density, a thermal/CVD stacked gate oxide decreases process-induced device degradation dramatically as compared with thermal gate oxide. Hot carrier injection stressing and Fowler-Nordheim stressing were performed to investigate the robustness of CVD stacked gate oxide. The effect of densification of the stacked gate oxide on electrical channel length was studied with supporting SEM analysis. An optimal value for the thickness ratio of CVD to thermal oxide for stacked gate dielectric was observed for minimum defect density of 150-AA gate dielectric.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>