A comparison of bridging fault simulation methods

Abstract

This study provides bridging fault simulation data obtained from the AMD-K6 microprocessor. It shows that: (1) high stuck-at fault coverage (99.5%) implies high bridging fault coverage; (2) coverage of a bridging fault by both wired-AND and wired-OR behavior does not guarantee detection of that fault when compared against a more accurate (transistor-level simulation) modeling method. A set of netname pairs representing bridging fault sites were extracted from layout and used for each fault modeling method. Results show that pattern generation should be driven by the most accurate modeling method when pursuing 100% bridging coverage, since less accurate methods will not necessarily converge to a high quality result.