A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical Simulations

Abstract

The optimization of grinding parameters for silicon wafers is necessary in order to reduce the likelihood of residual stresses and crack nucleation in the machined surface and improve the reliability of electronic packages. This paper describes numerical simulations performed to characterize the back grinding process for bare silicon wafers and through-silicon via (TSV) wafers using the finite element code ABAQUS. The grinding of the two wafer types was performed by simulating the motion of a diamond particle cutting through successive silicon and TSV layers. The silicon material was modeled using orthotropic elasticity and isotropic plasticity, while the copper vias were modeled using isotropic elasticity and Johnson-Cook plasticity. The polyethylene terephthalate (PET) material used as a backing tape for the silicon wafer was modeled using the Mooney-Rivlin hyperelastic model. The computed residual stresses and the plastic deformation in the superficial layer of the ground wafer were compared with experimental values and good correlation was observed. The simulation results can be used to better understand the local stresses and strain fields in both bare silicon and TSV wafers, and to quantify the effect of the copper vias on the wafer properties during and after grinding.