A comparative study of a deep-trench superjunction SiC VDMOS device

Abstract

A superjunction (SJ) SiC VDMOS device with a deep trench (DT-SJ SiC) is investigated and compared with conventional SiC VDMOS (C SiC) and SJ SiC VDMOS (C-SJ SiC) devices using numerical simulations. The DT-SJ SiC VDMOS device has an SJ drift region and a deep trench (DT) extending from the gate to the drain. The SJ provides a better trade-off between the breakdown voltage (BV) and specific on-resistance (Ron,sp), resulting in a high figure of merit (FOM = BV2/Ron,sp). The DT leads to a lower maximum gate oxide field (Eox,max) by breaking the restriction of Gauss’s law on the vertical electric field at the gate oxide interface. Moreover, the gate charge (Qg) and the gate–drain charge (Qgd) are dramatically reduced. The electrical characteristics of the DT-SJ SiC are studied and compared with the other two devices with the same dimensions. Compared with the C SiC, the BV and the maximum FOM are increased by 308 V and 3028 MW cm−2, respectively, while Ron,sp, Eox,max, Qg, and Qgd are decreased by 47.97 %, 26.98 %, 35.59 %, and 58.73 %, respectively. Compared with the C-SJ SiC, the BV and the maximum FOM are increased by 18 V and 116 MW cm−2, respectively, while Ron,sp, Eox,max, Qg, and Qgd are decreased by 1.04 %, 21.48 %, 40.63 %, and 61.91 %, respectively.