Abstract
Two solutions for the problem of fault simulation of digital integrated circuits and a comparison of their performance are presented. The first fault simulator is a serial simulator. Because of the efficiency of the logic simulation algorithm the results are quite good. The second is a differential fault simulator which takes advantage of the order in which the faults are simulated. These fault simulators will work in an automatic test pattern generation (ATPG) system which deals with combinatorial or sequential scan designed circuits considering the stuck-at-0, 1 fault model. An overview of ATPG systems and different methodologies used in fault simulation is also presented. In the description of the suggested approach, special emphasis is given to the basic logic simulator used to implement the fault simulators. Benchmarks have been developed on ISCAS circuits and were obtained in terms of CPU time, fault coverage and number of events, for a set of random vectors. >
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