Abstract
Purpose of this work is to present a new macromodelling approach for the simulation at the device level of large MOS integrated circuits, requiring only marginal modifications to be implemented in the widely used circuit simulator SPICE. This method results in a substantial saving in computing time and guarantees the same accuracy of SPICE. A prototype simulator based on this method has been developed and used to analyse several significant circuits. In addition, since the method is particularly suitable to be implemented in parallel computers, some results obtained with the CRAY-YMP/432 computer are provided.
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Schedule a callMore From: International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
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