A Single Event Effect Simulation Method for RISC-V Processor

Abstract

For accurately assessing the reliability of space application toward soft errors, this paper proposed a method of Single Event Effect simulation method for Large Scale Integrated Circuits (LSI). This simulation method divided into three levels: fault model, fault injection and target system simulation, which consists of a variety of simulation tools, such as TCAD, SPICE circuit simulator and analyzing tools of gate-level netlist. A 4-stage in-order RISC-V soft processor is used as the simulation target system. The simulation method has the following advantages: 1. It is a universal method of testing any large-scale integrated circuit including its peripheral components. 2. By input the gate-level net-list of the circuit and add the simulation stimulus, the method can get the simulation report automatically. 3. The soft error can be traced: The faulty node and the voltage waveform of the node can be reported intuitively.