A Compact Model Analysis of Layout Variation Impact on Mechanical Stress in Dielectrics

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The current industry trends towards reducing feature size and increasing integration density call for the use of copper (Cu) metallization and low permittivity (low-k) interlayer dielectrics (ILD). Low-k dielectrics are typically characterized by low mechanical strength, low hardness and high porosity (Blaine et al., 2002). The thermal mismatch stresses induced by the manufacturing process pose significant reliability challenges for the integration of Cu/Low-k interconnects because of the poorer mechanical characteristics of the low- k dielectrics (Cherault et al., 2005). Moreover, the geometry and the pattern of the metal lines have a significant impact on the thermomechanical stresses in multilevel interconnect structures, which in turn affect the interconnect reliability (Shen, 1999 and Yao et al., 2004). Interconnect processing, layout geometry and layout proximity effects can create regions of high stress concentrations and/or gradients in the interconnect structures employed in deep sub-micron technologies. These stress hot- spots are responsible for cracking and formation of voids in metal lines and the surrounding dielectric, thereby decreasing the overall yield (ogawa et al., 2002 and Lee et al., 2002). This paper presents a numerical analysis-based compact model approach to improve the manufacturability and reliability (design for manufacturing) of back-end-of-the-line (BEOL) structures, with emphasis on the dielectric reliability.