Low-k ILD reliability through chip-package assembly: Engineering appropriate stress tests and process certification criteria

Abstract

Inter-layer dielectric (ILD) materials used in silicon chip backend layers tend to be mechanically fragile, and the industry trend is towards ILD materials with even lower dielectric constants and fracture toughness. Flip-chip packaging with lead-free solder materials imposes significant thermo-mechanical stresses on these fragile ILD films due to the thermal expansion miss-match between the silicon chip and organic package. To guarantee low-K ILD integrity through chip-package assembly and reliability in use with adequate margin it is crucial to understand and quantify the sources of stress, their variability and use this information to define the right stress tests and success criterion. This paper will present a systematic study of the modulators of low-K ILD stress using empirical data from 45, 32 and 22nm Intel processes as well as finite element modeling. Key sources of variation in the silicon chip process as well as the chip-package assembly process will be examined and their effects on ILD stress will be quantified. This information will be used to assess the amount of over-stress needed to account for worst case manufacturing variation in silicon chip and chip - package assembly processes. Two approaches to characterization tests that provide the required over-stress will be discussed. The first approach is based on chip processing and package design skews to increase the ILD stress while the second approach relies on cooling the chip-package to below room temperature post-assembly in order to exaggerate the thermal expansion miss-match and over-stress the ILD layers. Process certification criteria to guarantee ILD reliability will be presented and optimized sampling plans to demonstrate that these goals are met will also be discussed.