A compact bipolar transistor model for very-high-frequency applications with special regard to narrow emitter stripes and high current densities

Abstract

In advanced silicon bipolar technologies very narrow emitter stripes can be realized. As a consequence, the transistors in high-frequency (h.f.) ICs should be operated at high current densities in order to obtain maximum operating speed. Therefore, in this paper a semi-physical compact transistor model is presented which is proven to be well suited for simulating analog h.f. ICs up to f T even in the high-current region. It is based on an improved version of the transistor model HICUM which has first been described in[1,2] and which was successfully applied for designing high-speed digital circuits. The model presented here, however, is not only superior in very-high-frequency applications but also in modeling narrow-emitter transistors. These advantages are obtained by accurately taking into account non-quasi-static transistor behavior, h.f. emitter current crowding, and emitter-periphery effects, as well as by improving the operating point dependence of basic parameters. Due to the physical nature of the model, the elements of the equivalent circuit can easily be calculated for arbitrary transistor geometries at arbitrary operating points and temperatures from a single set of specific electrical and technological data. This makes the model very well suited for circuit optimization. The compact model, which has been implemented in SPICE, was successfully verified by means of two-dimensional device simulations based on the doping profile of a real self-aligned double-polysilicon transistor. In order to be sure that verifying the compact model by device simulations replaces the measurements correctly, the model parameters were determined by device simulation too, but applying the methods used for experimental parameter extraction.