A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges

Abstract

Tunneling field effect transistors (TFETs) are playing a pivotal role in the unhindered progress of microelectronics industry into sub-micron and nanometer regime by efficiently replacing conventional MOSFETs by dint of their superior performance at such a low device dimension. In this research endeavor, we have incorporated the innovative gate engineering concept of continuously varying mole fraction in a binary metal alloy (BMA) gate electrode along the horizontal direction into a conventional TFET on buried oxide layer. The proposed BMA silicon-on-nothing (BMASON) TFET helps to tune the barrier at the source-channel junction, so that the band-to-band tunneling of the carriers occurs at a significant rate, thereby increasing the device ON current. However, device operation at such ultralow dimension will result in a considerably high electric field which inevitably impacts device performance due to hot carrier effect-induced localized charge trapping in the oxide region. This work presents an analytical model based on the Poisson’s equation and the Kane’s model incorporating the localized trapped charges at the oxide–silicon interface to explore the impact of localized charges on the performance of the proposed BMASON TFET in terms of surface potential, electric field and drain current characteristics. To validate our proposed model we have compared the results with 2D Sentaurus TCAD data and found good agreement between the two, thereby making this model suitable to design future charge-trapped memory devices based on TFET operation.