A Compact 65nm CMOS Sub-1-V All-MOSFET Voltage Reference with Low Average Temperature Coefficient of 13.9ppm/°C

Abstract

In this paper, we present a novel CMOS sub-1-V voltage reference design without any resistor or bipolar junction transistor. By forming a closed feedback loop, the temperature stability of the proposed voltage reference is significantly enhanced. In addition, a dedicated operational amplifier is introduced to improve the power supply rejection ratio (PSRR) and line regulation (LR). Moreover, the proposed voltage reference, which is implemented by using a 65nm 1.2V standard CMOS process, features a compact silicon area of 609$\mu m^{2}$. According to our 300 runs Monte Carlo simulation results, the average and minimum temperature coefficient (TC) from -40°C to 100°C is calculated to be 13.9ppm/°C and 4.2ppm/°C, respectively. The PSRR is reported to be 38dB and 61dB at DC and 10MHz, respectively. Meanwhile, the proposed implementation’s operational power supply range is from 0.9V to 2.6V, with a calculated line regulation of 2.29%/V.