Abstract
This paper presents a 38-54 GHz sub-harmonic up-conversion mixer in 65 nm CMOS process using derivative superposition third-order transconductance cancellation technique. The measurement results demonstrate -2.5 dB conversion gain and -11.7 dBm OP1dB at IF input frequency of 100 MHz and RF frequency of 41 GHz with relatively low power. The 3-dB RF bandwidth covers 38 to 54 GHz. The dc power consumption of the mixer is 8.5 mW. The improvement of OIP3 is 4 dB (from 0 to 4 dBm). The chip area of the proposed mixer is 0.8 × 0.55 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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