Design of 0.13 µm low power CMOS subharmonic mixer for DCR applications

Abstract

ABSTRACT This paper presents a design of 2.4 GHz folded subharmonic active mixer in TSMC 130 nm CMOS process for direct conversion receiver (DCR). To achieve the low supply voltage, the folded topology is adopted for the proposed subharmonic mixer. The complementary current reuse structure is used as RF transconductance stage where the biasing for the PMOS and NMOS transistors are self-biased by a resistor to support high conversion gain at low supply voltage. Frequency doubling operation is done by the mixing core which is driven by a quadrature local oscillator (LO) signals. The proposed mixer is designed and simulated using ADS (Advanced Design System) simulator with Cadence software. It produces 10.5 dB conversion gain, a single sideband) noise figure of 9.5 dB, 2 LO-to-RF isolation of 53 dB, LO-to-RF isolation of 117 dB, RF-to-IF isolation of 55 dB and IIP3 of −7.5 dBm. The quadrature LO subharmonic mixer consumes 824μW power from a supply voltage of 0.8 V. The proposed mixer is compared with existing subharmonic mixers. The comparison shows the proposed subharmonic mixer gives a good Figure of Merit.