A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems

Abstract

This paper presents new codes (and the related encoder/decoder scheme) to address the significant drawback of a phase change memory (PCM), namely that its write latency is significantly longer than the read latency. The proposed scheme improves over existing schemes by reducing the average write latency and the number of SET operations in a PCM. A new code, referred to as the write time speed-up (WTS) code is introduced; WTS improves over existing schemes previously employed for this operation, i.e., the flip-N-write and the write-once-memory (WOM) code. In the proposed WTS code, multiple codewords correspond to every information word; the codewords are selected to reduce the number of SET operations (each requiring a longer time than the RESET operation in a PCM). The proposed scheme targets a reduction in SET operations, by executing them only when required, i.e., so making the SET operations to occur irregularly with the write operations. Simulation results are provided using an embedded benchmark suite; they show that the proposed scheme incurs in a shorter average write time than the flip-N-write scheme as well as the existing scheme with the WOM code when parallel data is provided. Encoding and decoding times for the proposed scheme are significantly shorter than the read and write latencies of a PCM. Moreover, the hardware overhead (in the area for LUT-based implementations) for the encoder and decoder of of WTS code is significantly smaller than the PCM system size, thus making the proposed design viable for implementation.