A CMOS voltage reference based on weighted ΔV/sub GS/ for CMOS low-dropout linear regulators

Abstract

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-μm CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0°C). The occupied chip area is 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 μA. A typical mean uncalibrated temperature coefficient of 36.9 ppm/°C is achieved, and the typical mean line regulation is ±0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).