A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement

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This paper presents a 53–61 GHz low-power charge-pump integer-N type-II PLL, employing a class-D V-band voltage control oscillator. Transistors in the VCO enter deep triode region to achieve low DC power and phase noise. Pros and cons of the triode region are studied in this paper. We have explained how this region has been accurately exploited to reduce the phase-noise. This is unlike the general notion that the triode region degrades phase-noise performance in oscillators. The phase locked loop is fabricated in a standard 65 nm CMOS process. The VCO consumes the minimum power of 10.6 mW from 0.8 V supply. The PLL achieves a wide tuning range of 13% from 53.35–60.83-GHz and a phase noise of −88 dBc/Hz at 1–MHz offset, while consuming a minimum DC power of 48 mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.