Abstract
A new Operational Floating Current Conveyor (OFCC) circuit is presented. The presented OFCC circuit is the first CMOS OFCC circuit which is suitable for low power VLSI applications. The proposed OFCC circuit is designed to achieve two design goals. The first designed circuit is a low power consumption OFCC circuit (LBW design) while the second design is a high bandwidth OFCC circuit (HBW design) with power consumption sacrifice. Both designs are designed and simulated using TSMC 90nm technology kit in Cadence.
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