Abstract

The paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three Operational Floating Current Conveyors (OFCCs) and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA) is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematicThe paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three operational floating current conveyors (OFCCs) and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA) is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematic.

Highlights

  • The Operational Floating Current Conveyor (OFCC) [1], [2] is a versatile active building block which provides flexibility to the circuit designer

  • It is clear from the above discussion that only topology [27] provides proper input and output impedance levels and does not require additional circuitry for impedance matching

  • The aim of this paper is to present an OFCC based Transimpedance Instrumentation Amplifier (TIA) offering proper input/output interface

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Summary

Introduction

The Operational Floating Current Conveyor (OFCC) [1], [2] is a versatile active building block which provides flexibility to the circuit designer. Tab. 1: Characteristics of available instrumentation amplifiers It is clear from the above discussion that only topology [27] provides proper input and output impedance levels and does not require additional circuitry for impedance matching. The aim of this paper is to present an OFCC based TIA offering proper input/output interface. It uses three active blocks and four resistors i.e. same number of active blocks as [27] and the lesser passive components than [27]. Both input and output impedances of proposed topology are low.

Proposed Circuit
Non Ideal Analysis
Simulation Results
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