A CMOS Class-E Power Amplifier With Voltage Stress Relief and Enhanced Efficiency

Abstract

This paper proposes a class-E power amplifier (PA) with double-resonance circuit to reduce voltage stress on CMOS transistors. The voltage waveform applied to the CMOS transistor is shaped by harmonic control and the transistors are relieved from breakdowns. A negative capacitance is also implemented for efficiency enhancement, compensating for surplus capacitance from parasitic components on the drain node. Thus, nominal class-E operation is restored and high efficiency is achieved. We present a cascode differential class-E RF PA that is fabricated using a 0.13-¿ m CMOS technology that delivers 31.5-dBm output power with 54% drain efficiency and 51% power-added efficiency at 1.8 GHz.