Abstract

A CMOS integrated 4-channel capacitive harmonic rejection baseband receiver and 4×4 MIMO analog core spatial filter demonstrate >65dB harmonic folding rejection over 48MHz, and >48.5dB signal separation across 3MHz baseband. The 65nm CMOS IC occupies 3.27mm2 active area and consumes 0.67mW–1.28mW.

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