Frequency-translation techniques for interference-robust software-defined radio receivers

Abstract

There has been a growing demand for wireless communications and diverse communication standards have been developed. A software-defined radio (SDR) consists of radio hardware which is programmable by software to support many standards and even emerging ones. Several technical challenges exist to realize a SDR. This thesis focuses on frequency translation (FT) techniques and addresses two key challenges of SDR receivers: the robustness to out-of-band interference (OBI) and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the limitations of existing FT techniques and proposes new circuit-and-system techniques to improve SDR receivers. Fundamental differences between various FT techniques are highlighted by means of a classification and comparison of mixing and sampling. The suitability of RF-mixing and RF-sampling receivers to SDR is evaluated. Due to some narrowband properties, existing RF-sampling techniques are not suitable for SDR receivers. To address this issue, a discrete-time (DT) mixing technique is proposed which performs mixing in the DT domain after RF sampling. It makes RF sampling more suitable to SDR receivers due to its wideband properties. A 200-to-900MHz DT-mixing downconverter with 8-times oversampling and 2nd-to-6th harmonic rejection (HR) is implemented in 65nm CMOS. To construct a complete RF-sampling receiver, a tunable LC filter and a linearized LNA are used before a DT-mixing downconverter. The RF-sampling receiver achieves a minimum NF of 0.8dB and improves HR by 30dB compared to the downconverter alone. To be more robust to OBI, two FT techniques are proposed: one to improve the out-of-band linearity and the other to make the HR robust to mismatch. A low-pass blocker filtering technique makes voltage gain not at RF but at baseband simultaneously with low-pass filtering to attenuate OBI. A two-stage polyphase HR technique performs HR in two cascaded stages to dramatically improve amplitude accuracy. To also achieve high phase accuracy, a simple and accurate frequency divider is proposed. A 65nm-CMOS receiver shows +3.5dBm in-band IIP3 and +16dBm out-of-band IIP3. More than 60dB HR ratio is measured over 40 chips. The multiphase clock generator works up to 0.9GHz while the -3dB RF bandwidth is up to 6GHz.