A CMOS 0.35-μm, 3.3-V PLL synthesizer for Bluetooth transmitter

Abstract

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 2.4 and 2.479 GHz with 1-MHz channel spacing and settles in approximately 100 μs is presented. The highlights of the topology are an N integer PLL architecture that operates with 1-MHz reference frequency and a passive discrete-time loop filter. The output signal is generated by a simple cross-coupled LC VCO and divided by a programmable frequency divider. The proposed PLL is designed to be employed as a synthesizer for Bluetooth transmitter in a low-cost CMOS technology. Simulated in 0.35-μm CMOS process, the PLL consumes 9.87 mA from a 3.3 V supply and achieves phase noise of −128.68 dBc/Hz at 3 MHz offset and spurs of −67 dBc at 3 MHz.