A CML Ring Oscillator-Based Supply-Insensitive PLL With On-Chip Calibrations

Abstract

A 1.5–2.5 GHz current-mode logic (CML) ring oscillator-based supply-insensitive phase-locked loop (PLL) employing two different topologies of CML ring oscillators that compensate for the supply variations is presented. In addition, an on-chip calibration scheme is designed to ensure the voltage-controlled oscillators (VCOs) to operate at the optimum operating point where the PLL achieves nearly the best power supply rejection. This work shows more than 96% reduction in supply sensitivity of VCOs compared with the conventional topology. In addition, the sinusoidal jitter is improved by at least 70% closed-loop with the on-chip calibrations. The chip was fabricated in SMIC $0.18~\mu{\rm m}$ CMOS process.