A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests

Abstract

A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65nm CMOS technology. It demonstrates frequency syntheses of 1.68GHz to 3GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5ps to 9.4ps with a 3.125ps step resolution.