Clock Generation and De-skewing

Abstract

A phase-locked loop (PLL) or a delay-line loop (DLL) is a programmable, frequency synthesizer macro cell designed specifically for clock generation or de-skewing. A PLL or DLL can be used to adjust dynamically the edges of the output clock to match those of the input clock. PLLs can be used to double or multiply the input clock frequency, such as outputting the clock with 2X and 4X clock frequencies. DLLs, which are also called de-skewing buffers, are used to compensate the clock skew resulting from the delay mismatch in the clock network. The difference between the PLL and the DLL is that the DLL uses only the inverter delays, while the PLL contains the analog VCO (voltage controlled oscillator) for the clock phase adjustment. Section 5.1 introduces an on-chip clock generator. Section 5.2 presents the PLL characterization results. Section 5.3 provides the PLL floorplan guidelines. Section 5.4 describes DLL circuits and de-skewing buffers. Section 5.5 shows an on-die clock shrinking technique for silicon debug. The detailed circuits of the PLL interior components (charge pump, VCO, delay matching, divider, etc.) are not included in this book. They can be found in a good reference for PowerPC microprocessor [89].