A clock and data recovery circuit with wide linear range frequency detector

Abstract

As the data rate increases above Gb/s, the design of a clock and data recovery (CDR) circuit becomes a great challenge. A 3.125-Gb/s CDR is proposed to shorten the frequency acquisition time by employing a wide-linear-range frequency detector. Fabricated in a 0.18-μm 1P6M CMOS technology, the output jitter of this proposed CDR is measured as 70ps (peak-to-peak) and 8.3ps (rms). The measured bit-error rate (BER) is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> −1 PRBS. The proposed CDR occupies a chip area of 0.61 mm × 0.61 mm and dissipates 61mW from a single 1.8-V power supply.