A circuit implementation for dynamic thermal management techniques

Abstract

Dynamic thermal management (DTM) techniques like fetch-throttling, register rename throttling and register file occupancy throttling have some favorable features compared to dynamic voltage and frequency scaling (DVFS) technique for multi-core chip design. This paper presents the circuit implementations for the above mentioned non-DVFS techniques. A power-performance analysis of the implemented circuits has been performed to evaluate the performance of these DTM techniques, and to estimate the power overheads and the performance loss due to the inclusion of these DTM circuits. CPU bound workloads are used to simulate the proposed circuits.