Abstract
A chip-level single-event latchup (SEL) estimation methodology is introduced, and its accuracy is demonstrated on the test vehicles manufactured in a state-of-the-art technology for various process options. Novel test structures have been designed and built to make them accessible to accelerated beam testing for the purpose of calibrating the SEL rate as a function of layout design style and use condition. The calibrated model and the SEL assessment strategy are capable of accurately accounting for variations in circuitry and layouts across complex products. The 64-MeV monoenergetic proton and broad-spectrum neutron beam testing results establish that the novel compact model accurately projects full-chip SEL rates, and hence, it can be used to guide layout optimizations and mitigate (or eliminate) component-level SEL rates.
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