A Charge Balanced Neural Stimulator Using Chopped Anodic Pulse Control

Abstract

This paper presents a novel neural stimulator integrated circuit (IC) that utilizes a chopped pulse waveform for higher power efficiency and active charge balancing. The proposed IC, designed using $0.18\mu m$ standard CMOS process, consists of electrical stimulator circuit and active charge balancing circuit. Transistor stacking technique is employed in the stimulator circuit to protect the output current driver devices and charge balancing devices from high voltage stress. The proposed active charge balancing circuit uses a very simple digital logic circuit that consists of comparator and D-latch which can perform safe charge balancing by using the chopped anodic pulse control.