A challenge of 45 nm extreme low-k chip using Cu pillar bump as 1<sup>st</sup> interconnection

Abstract

In this study, Cu pillar bump is firstly built on FCCSP with 65 nm low k chip. 7 DOE cells are designed to evaluate the effects of Cu pillar height, Cu pillar diameter, PI opening size and PI material on package reliability performance. No obvious failure is found after package assembly and long-term reliability test. The packages are still in good shape even though the reliability test is expanded to 3x test durations With the experiences of Cu pillar bump on 65 nm low k chip, Cu pillar bump is again built on FCBGA package with 45 nm ELK chip. White bump defect is found after chip bond via CSAM inspection, failure analysis shows that the white bump phenomenon is due to crack occurs inside ELK layer. A local heating bond tool (thermal compression bond) is used to improve ELK crack, test results illustrate ELK crack still exists, however the failure rate reduces from original 30%~50% to 5%~20%. Simulation analysis is conducted to study the effect of PI opening size and UBM size on stress concentration at ELK layer. Small PI opening size can reduce stress distribution at ELK layer. On the contrary, relatively large PI opening size and large UBM size also show positive effect on ELK crack. Assembly process and reliability test are conducted again to validate simulation results, experiment data is consistent with simulation result.