A Cellular Automata Based BIST for Detecting NPSFs in High Speed Memories

Abstract

Built-in-self-test (BIST) in memory is considered as most cost effective method for memory testing. In this work, we propose a cellular automata (CA) based BIST architecture to detect neighborhood pattern sensitive faults (NPSFs) in high speed memories. For implementation of the proposed CABIST, we employ 5-neighborhood periodic boundary CA (PBCA). Theory has been developed for two special classes of PBCA - single length cycle single attractor CA (SACA) and single length cycle two attractor CA (TACA) employed for the design. The proposed CABIST efficiently detects all NPSFs in memory devices at a lower cost compared to existing schemes.