Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols

Abstract

In embedded SoC applications, the demand for integration of heterogeneous processors on a single chip is increasing. On-chip heterogeneity allows different processors to employ different cache coherence protocols which in turn add difficulties in the task of integrating different coherence protocols as well as realizing the task of coherence verification. This work first proposes an efficient mechanism for integrating update based as well as invalidation based coherence protocols in a heterogeneous Chip Multiprocessors (CMPs) cache system and then realizes a coherence verification logic to verify cache coherency in such a system. The verification logic design is based on the modular structure of Cellular Automata (CA). The special class of CA, referred to as SACA (single length cycle single attractor CA) has been employed to identify the inconsistencies in cache line states computed by cache coherence controller (CC). The simple hardware implementation of the CA based design realizes quick decision on the cache coherency with high accuracy.