Abstract
The need for higher circuit density on a integrated circuit (IC) with high pin count requires a large substrate size package to accommodate its wiring. This paper presents issues, approaches, and solutions for a high pin count (447 pins) microprocessor ceramic packaging with a focus on the package cracking. The effects of printed circuit board thickness, package standoff height, and environmental conditions on high pin count ceramic pin grid array (CPGA) package cracking are reviewed and discussed.
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