A Case Study: Low Power Design-for-Testability Features of a Multi-Core Processor Godson-T

Abstract

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical cores. Since the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processors. In this paper, we use the modular design methodology and scaleable design-for-testability (DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further more. The experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.