Abstract
A capacitor-free control scheme is presented for primary-side regulation (PSR) flyback converter to reduce cost and increase system reliability. Compared to conventional voltage compensation, the proposed converter using an error amplifier sampling scheme reduces zero and pole as load decreases, and thus, the stability of the system makes significant strides especially under light loads. The proposed controller provides high stability and fast load transient response even in capacitor-free scheme. Besides, a ramp voltage with reduced slope is allowed to pursue a wider output load range and further reduce switching frequency for lighter load. The proposed controller is implemented in 0.18- μ m 100-V BCD process and occupies a die size (with pads) of 1.3 × 1.2 mm2. The experimental results show that the deviations of output voltage are within ±0.35% under different inputs and loads while the peak power efficiency of 87.3% is achieved.
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