A Cache Architecture for Extremely Unreliable Nanotechnologies

Abstract

In the drive to create ever smaller transistors, conventional silicon CMOS devices are becoming more difficult to fabricate reliably as process size shrinks. New technologies are being investigated to replace silicon CMOS. While offering greater numbers of devices per unit area, all of these technologies are more difficult to fabricate, and more likely to fail in operation than current technologies. Nanotechnology research has identified the need for fault and defect tolerance at the architectural level so that future devices can be used in large-scale electronics circuits. This paper examines the problem of creating reliable caches using extremely unreliable technologies. We incorporate support logic (i.e., control, datapath, and self-test logic) into the analysis, and propose a novel Content Addressable Memory-based design incorporating best practice fault tolerant design techniques. The design requires 15 times the number of devices of a conventional design, but enables the use of device technologies with defect rates higher than 10-6, a three order of magnitude improvement over non-fault tolerant designs