Abstract
We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic-resolution.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.