A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology

Abstract

A fully integrated broadband power amplifier (PA) is implemented in a standard 45-nm CMOS SOI technology. The PA is designed using a dynamically biased stacked SOI transistor approach, which constructively adds drain-source voltage signals of individual transistors while keeping their gate voltages within source and drain voltage limits. The design overcomes both low gate-oxide breakdown and low source-drain reach through voltages of nanoscale CMOS transistors. The number, size, and topology of transistors in the stack are optimized to deliver a relatively high linear output power over a wide range of frequencies. The amplifier under a supply voltage of 4.5 V measures a flat gain of 6 dB with -1-dB bandwidth of 6 to 26.5 GHz ( X-band to K-band). At 18 GHz, the PA under a supply voltage of 7.2 V measures a saturated output power (PSAT) of 26.1 dBm ( ~ 400 mW), a linear output power (P1 dB) of 22.5 dBm, and a peak power-added efficiency (PAE) of 11%. With a lower power supply voltage of 4.5 V, the PAE increases to more than 20% and stays above 17% with relatively constant PSAT and P1 dB for several measured frequencies in the range of 6 to 20 GHz. The PA occupies an active chip area of only 0.16 mm2.