A Broadband Logarithmic Power Detector in 0.13-$\mu$m CMOS

Abstract

A broadband logarithmic (log) power detector with a wide dynamic range has been developed using a 0.13 μm CMOS process. The proposed power detector consists of three signal amplification and rectification branches combined in parallel for broadband operation. The required linearity and dynamic range are provided by high-linearity rectifier design using active degeneration technique. The fabricated power detector chip has a size of 1.0 mm × 0.75 mm and consumes 35.2 mW. The power detector shows a dynamic range wider than 43 dB with ± 1 dB log error up to 14 GHz. Over 50 dB dynamic range is achieved at 16 GHz with a slightly higher log error of ± 1.5 dB.