A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)

Abstract

The performance of elliptic curve cryptosystems is primarily determined by an efficient implementation of the arithmetic operations in the underlying finite field. This paper presents a hardware architecture for a unified multiplier which operates in two types of finite fields: GF(p) and GF(m). In both cases, the multiplication of field elements is performed by accumulation of partial-products to an intermediate result according to an MSB-first shift-and-add method. The reduction modulo the prime p (or the irreducible polynomial p(t), respectively) is interleaved with the addition steps by repeated subtractions of 2p and/or p (or p(t), respectively). A bit-serial multiplier executes a multiplication in GF(p) in approximately 1.5ċ⌈log2(p)⌉ clock cycles, and the multiplication in GF(m) takes exactly m clock cycles. The unified multiplier requires only slightly more area than that of the multiplier for prime fields GF(p). Moreover, it is shown that the proposed architecture is highly regular and simple to design.