A BIST scheme for the detection of path-delay faults

Abstract

Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a circuit. Unlike stuck-at faults which can be detected using ATE at lower speed, test for path-delay faults require ATEs that can run at the clock frequency of the circuit under-test. However, with ever-increasing circuit-speed and complexity, ATEs are unable to keep up with this growing trend. Moreover running deterministic tests for timing related defects on expensive ATEs for high-speed circuits consume enormous test application time. In this paper, we propose a BIST methodology for path-delay faults in sequential circuits. The proposed technique is based on an existing BIST architecture for stuck-at faults such that timing faults in a circuit can also be addressed with minimum additional effort. A new clocking scheme along with a novel technique for placing observation points that increases the fault coverage for path-delay faults is presented. Experimental results on some benchmark circuits show high path-delay fault coverage for sequential circuits.