Abstract
An emitter-coupled logic (ECL) 100K compatible 18K-gate masterslice has been developed. A variable-size-cell (VSC) approach is proposed to reduce nonutilized elements in the ECL gate array. The concept of the VSC is to implement logic circuitry not by the usual macrocells but by newly developed cellular units. The unit is constructed using three transistors and four polysilicon resistors. By utilizing 1.2-/spl mu/m salicide base contact technology, the intrinsic gate delay is 150 ps at a power consumption of 2.4 mW. A 32-bit multiplier has been implemented as an application. Compared with conventional cell structures, a 20% higher effective gate density is achieved.
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