A &amp;#x2212;1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology

Davide Rossi,Antonio Pullini,Igor Loi,Michael Gautschi,Frank Kagan Gurkaynak,Luca Benini,Philippe Flatresse

doi:10.1109/s3s.2015.7333483

A &#x2212;1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology

Davide Rossi, Antonio Pullini + Show 5 more

Open Access

https://doi.org/10.1109/s3s.2015.7333483

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Publication Date: Oct 1, 2015
Citations: 15	License type: other-oa

Affiliation: ETH Zurich, University of Bologna, STMicroelectronics (France)

#Body Bias #28nm UTBB FD-SOI + Show 8 more

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Abstract

A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate “on-demand” on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and −1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419μW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance.

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