Abstract
This paper presents the design of a frequency quadrupler which operates at 116 GHz in 130 nm BiCMOS process. The quadrupler consists of two-stage cascaded frequency doublers with two wideband baluns. The measured peak output power is 8.5 dBm at 116 GHz, and the 3-dB bandwidth is from 99 GHz to 132 GHz. The frequency quadrupler consumes 24 mA DC current from a 3.3 V power supply. The peak DC-to-RF efficiency of the quadrupler is 8.8%. To the best of the authors knowledge, this is the highest reported output power and efficiency achieved by frequency multiplier without a dedicated power amplifier in this frequency range with silicon processes.
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