A 52–65 GHz Frequency Quadrupler With Low Conversion Loss and High Harmonic Rejection Ratio in 28-nm CMOS

Abstract

This brief presents a 52-65 GHz frequency quadrupler with low conversion loss and high harmonic rejection ratio based on 28-nm bulk CMOS process. The frequency quadrupler includes two stages balanced frequency push-push doublers (PPD) cascaded with common-gate buffers. A series LC pair is placed between the PPD and the buffer of the first stage, which not only improves the conversion gain, but also suppresses the unwanted fundamental signals. A filter-integrated matching network is designed as the output matching network to reject undesired harmonics. As a result, the proposed design exhibits advantages in conversion gain and harmonic rejection ratio. The measured peak output power is -1.8 dBm and the output power 3-dB bandwidth is 52-65 GHz when the input power is 0 dBm. The even and odd harmonics rejection ratios are better than 35 dBc and 45 dBc, respectively, which can be used in high-performance mm-Wave LO chain.