A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer

Abstract

This work presents a direct 48–1-V DC–DC point-of-load (POL) converter for efficient high-voltage conversion. Conventional hybrid topologies face limitations of large number of off-chip components and limited operation ranges. By combining the three-level buck converter with the hybrid Dickson converter, the proposed topology shows ten times reduced switching voltages with only five off-chip flying capacitors—a near 50% reduction compared with prior works. The reduced voltage stress enables using low-voltage on-chip Si power devices, further reducing the number of off-chip switches. A gradient descent run-time optimizer along with a hybrid current-sensing analog-to-digital converter (ADC) is proposed to dynamically optimize converter’s efficiency, improving the operation range. Thus, the proposed design overcomes the limitations of previous hybrid converters. The prototype was fabricated using a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> Bipolar-CMOS-DMOS (BCD) process. The converter achieves an input voltage of 48 V and an output voltage of 0.7-to-1 V with a maximum load capacity of 12 A. The measured peak efficiency is 90.4% at 48–1-V conversion, and the maximum efficiency improvement is 16.7% with the proposed optimization circuits.