A 8.9 mW, 0.6–2 GHz fast locking delay-locked loop using dual delay lines with phase blender

Abstract

This paper presents a fast lock mixed-mode DLL (delay-locked loop). The architecture of the proposed DLL uses a coarse-step TDC (time-to-digital converter) scheme and an analog feedback loop, which is a fine step. A simple technique to phase blend a DDL (dual delay lines) with phase difference in coarse step improves the coarse time resolution without additional lock time. Based on this improved time resolution, the second fine step can be completed to provide fast lock time, high accuracy and low power consumption. The proposed DLL operates in the clock frequency range of 0.6GHz to 2GHz in 65nm CMOS technology. The simulated lock time of the DLL can be locked within 10 clock cycles at the provided operating frequency. Power consumption is 8.9 mW at 2 GHz from the supply voltage of 1.0-V.