A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

Ying-Zu Lin Ying-Zu Lin,Chao-Hsin Lu Chao-Hsin Lu,Shan-Chih Tsou Shan-Chih Tsou,Chih-Hou Tsai Chih-Hou Tsai

doi:10.1109/vlsic.2016.7573536

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

Ying-Zu Lin Ying-Zu Lin, Chao-Hsin Lu Chao-Hsin Lu + Show 2 more

https://doi.org/10.1109/vlsic.2016.7573536

Copy DOI

Publication Date: Jun 1, 2016

Citations: 24

#Background Timing-skew Calibration #Peak SNDR + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm2. From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.

Full Text