A 79-GHz Adaptive-Gain and Low-Noise UWB Radar Receiver Front-End in 65-nm CMOS

Abstract

A 79-GHz adaptive-gain and low-noise ultra-wideband radar receiver RF front-end integrated circuit in 65-nm CMOS is presented in this paper. The receiver consists of an adaptive-gain low-noise amplifier (AGLNA) and a ${ g}_{ m}$ -boosted sub-harmonic mixer (SHM). The proposed AGLNA controls the gain with adaptive biased circuits, which lowers the gain as the received signal power increases to provide wide dynamic range to the radar receiver without any external controls. We analyzed the input impedance of a cascode amplifier with a parallel resonant inductor, which improves the noise figure. The proposed ${ g}_{ m}$ -boosted SHM uses a transformer-based feedback network with NMOS bleeding circuits to provide a high conversion gain. The SHM was designed to use a differential local oscillator (LO) signal to have a simple structure and operate at low LO power. The measured conversion gain range was from 16 to $-{\hbox{7.5 dB}}$ with a received power range from $-{\hbox{45}}$ to $-{\hbox{5 dBm}}$ at 79.5 GHz. The measured noise figure was 10.5 dB and the measured 2LO-to-RF isolation was 70 dB. The chip area is ${\hbox{0.47}}\times {\hbox{1.23}}~{\hbox{mm}}^{2}$ .